Field of the Invention
The present invention relates to a non-volatile memory device, and an operation method and a fabrication method thereof, and more particularly to a NAND flash memory having a zigzag body wiring, and an operation method and a fabrication method thereof.
Description of Related Art
In recent years, in order to overcome the issues of NAND flash scaling, emerging memories and three-dimensional memories have been aggressively investigated. With no happening, the delay of word lines and/or bit lines limits the development of a memory controller.
At the upper and lower lines in FIG. 1, there are the cross-sections of bit lines. The distance between neighboring bit lines is wider at the upper lines than at the lower lines. The number of bit lines per unit space is larger at the lower, but the parasitic capacitance which causes the bit line delay exists. The self-align shallow trench isolation SA-STI, which is an important invention for the device scaling of NAND flash, greatly enhances the parasitic capacitance between neighboring bit lines. Therefore, the bit line delay has become notable with the scaling. At the upper and lower lines in FIG. 2, there are the cross-sections of word lines. The distance between neighboring word lines is wider at the upper lines than at the lower lines. The number of word lines per unit space is larger at the lower, but the parasitic capacitance which causes the word line delay exists.
To lower the bit cost, the cell-to-cell space is shrunk as the memory cell is miniaturized. Accordingly, the parasitic capacitance between neighboring word lines is increased with the device scaling of NAND cells. Therefore, the word line delay has become notable with the scaling.